Base-band receiver noise is always dominated by a channel selecting filter with embedded programmable gain amplifier (PGA) function. To alleviate a dynamic requirement of a backend analog-to-digital converter (ADC), a blocker rejection is conventionally designed to be second or third order. However, the noise reduction is always compromised with the operational amplifier stability in a power inefficient manner, especially in the receiver sensitivity test.
For a continuous time delta-sigma modulator, even if quantization noise can be eliminated by noise coupling or high oversampling ratio, circuit noise is still troublesome because of low efficiency of noise reduction. Generally, large circuit size and high operating current are common solutions to alleviate this problem. However, these common solutions need more manufacturing cost or power consumption.